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Future Electronics Egypt

74HC90 (Decade, Divided by  twelve AND binary counter- 4-BIT Binary Counter)

74HC90 (Decade, Divided by twelve AND binary counter- 4-BIT Binary Counter)

LE 7.00


high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five  section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9)

BCD Decade (8421) Counter — The CP1 input must be externally connected to the Q0 output.

The CP0 input receives the incoming count and a BCD count sequence is  produced.


Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. The input count is then applied to the CP1 input and a divide-by-ten square wave is obtained at output Q0

logic sympol

Specifications

  • No. of Pins: 14
  • Operating Temperature Range:0°C to +70°C
  • Supply Voltage Range: 4.75 V to 5.25V
  • Package: DIP-14  
74hc90 top view

 Symbol

pin

Description

CP0

   1

Clock (Active LOW going edge) Input to
÷2 Section

CP1

   14

Clock (Active LOW going edge) Input to
÷5 Section

MR1,MR2

   2,3

Master Reset (Clear) Inputs

MS1,MS2

   6,7

Master Set (Preset-9, LS90) Inputs

Q0

   12

Output from ÷2 Section 

Q1,Q2,Q3

  9,8,11

Outputs from ÷5 sections

NC

 4, 13

data inputs source 2

VCC

    5

supply voltage

 

Notes

- The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
Temperature Ranges.
- The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device-

-1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

-To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

For 74HC90 Datasheet Click Here

 

 

 

 

 

 

 

 

 



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